FIG. 1 shows a block diagram of a conventional circuit capable of receiving and processing broadcasted multi-channel multi-media data. The circuit includes a stand-alone demodulation chip 110 and a stand-alone multi-media processor chip 120. The demodulation chip 110 demodulates received broadcasted multi-media data, and transmits the demodulated data to the multi-media processor chip 120 for further processing, to generate video signals and/or audio signals. These signals are displayed by a display 130 and a speaker 140. Such circuit may be used in, e.g., mobile phone, PDA (personal digital assistant), and mobile television. The broadcasted multi-media data may be, e.g., wireless Internet data, television signals, etc.
In this conventional structure, external RF (radio frequency) signals are received and processed by an RF tuner 101 for frequency-down conversion. The processed analog signals are transmitted to an ADC (analog-to-digital converter) 111 to be converted to digital signals, and further demodulated by an OFDM demodulator (Orthogonal Frequency Division Multiplexer demodulator) 112. Afterwards, under the control by a controller 113, the digital signals are stored in an SRAM (static random access memory) 118 according to the address generated by a data interleaving address generator 114. For error correction purpose, data should be stored and read from different directions; the data interleaving address generator 114 serves the function for determining the addresses to read and store data. For details of memory interleaving, please refer to U.S. Ser. No. 11/581,118 filed by the same applicant. The data stored in the SRAM 118 are subject to error correction, and stored back to the SRAM 118. Thereafter, under the control by the controller 113, the error-corrected data are transmitted to the multi-media processor chip 120 for further processing. The two chips 110 and 120 communicate with each other through an SPI (serial peripheral interface).
Typically, the multi-media processor chip 120 includes both a DRAM (dynamic random access memory) 128 and an SRAM 129; they communicate with other parts of the circuit via a memory control interface 127. A video decoder 122 reads data through the control interface 127, decodes the data, and outputs the data via a display controller 126, to display them on the display 130. In one instance, the display 130 is a liquid crystal display panel; however it can be any other display device. On the other hand, an audio decoder 124 also reads data through the control interface 127, decodes the data, and outputs the data to the speaker 140. For better visual effect, preferably, the chip 120 further includes a JPEG encoder/decoder 124 for compressing/decompressing video or graphic files; and an image processor 125 for processing display contrast, color, brightness, etc.
When the multi-media data are broadcasted in multiple channels, such as television signals, a user would like to switch among the multiple channels to select a preferred program. In order to display the content of a channel instantly and smoothly without any perceivable delay as the user switch to that channel, the data broadcasted through channels that are not presently being watched by the user, e.g. the previous and next channels or even more, are also downloaded, stored, and error-corrected, so that the data can be ready to display as the user switch to that channel.
In the above-mentioned conventional circuit structure, data in every channel that are received have to be subject to complete error correction in the demodulation chip 110, and then transmitted to the multi-media processor chip 120. However, the two chips 110 and 120 communicate with each other in a serial manner, i.e., with a narrow bandwidth; thus, the overall processing speed is not optimum. In addition, of all channels of data stored in the SRAM 118, only one channel is useful. Due to cost concern, the capacity of the SRAM 118 has a limitation. In other words, because of the limited capacity of the SRAM 118, the number of channels allowed to be stored in the SRAM 118 is also limited; thus, when a user arbitrarily switches to a randomly selected channel, delay is unavoidable.
In view of the foregoing, the present invention proposes a multi-channel multi-media integrated circuit to overcome the drawbacks in the prior art.